Low Power Design, Power Optimization, Finfet, Dynamic Voltage Scaling (DVFS)
Abstract
The rapid development of integrated circuit technology has made the design of low-power circuits a major concern in this field. Power consumption limits the prolonged operation of high-performance computer systems, affects system performance and heat dissipation, and shortens the operating lifespan of portable devices. The fundamental causes of power consumption, including static, short-circuit, and dynamic power consumption, are thoroughly examined in this work, which focuses on the design of low-power digital integrated circuits. Power and voltage designs, DVFS (dynamic voltage and frequency scaling), and closed-loop clocking are some of the tactics for implementing low-power technologies that are also discussed. In addition, new ultra-low power designs such as field-effect transistors (FETs), semiconductor organic integrated circuits (SOIs), and tunneling field effect transistors (TFETs) are shown, and their usefulness is shown by way of an example of a Bluetooth 5.0 system-on-chip (SoC) application. Future developments in low-power design will guarantee ongoing innovation in high-performance electronic systems by optimizing device layouts and making use of new materials.
